1. Field
The memory control circuit, delay time control device, and delay time control method relate to a technique for controlling read/write operations for a plurality of memories to which a clock signal line is wired through the daisy chain connection, as in, e.g., a DDR3 memory interface, by supplying a clock signal through the clock signal line.
2. Description of the Related Art
Recently, the DDR3 (Double Data Rate 3) memory interface has been standardized as standards of a DRAM (Dynamic Random Access Memory) by JEDEC (Joint Electron Device Engineering Council) (see, e.g., JDEC STANDARD (JESD79-3; DDR3 SDRAM Standard). Unlike the hitherto practiced DDR (Double Data Rate) memory interface and DDR2 (Double Data Rate 2) memory interface (see, e.g., Japanese Laid-open Patent Publication No. 2003-99321, No. 2005-78547, and No. 2005-209168), the DDR3 memory interface employs fly-by topology for connection between a memory controller and a DIMM (Dual Inline Memory Module).
FIG. 1 is a block diagram showing a configuration example of the recently proposed DDR3 memory interface, and FIG. 2 is a block diagram for explaining a write leveling operation in the DDR3 memory interface.
As shown in FIG. 1, for example, the fly-by topology is configured such that a signal line for each of a clock signal CK, an address signal Add and a command signal CMD is wired from a memory controller 90 to a plurality (number n) of SDRAMs (Synchronous Dynamic Random Access Memories) 92-1 to 92-n (n is a natural number of 2 or more) on a DIMM module 91 through the daisy chain connection. On the other hand, data signal lines for data signals DQ and data strobe signals DQS are wired from the memory controller 90 to the plurality of SDRAMs 92-1 to 92-n on the DIMM module 91, respectively.
In the following description, regarding characters denoting the SDRAMs, when one among the plurality of SDRAMs needs to be specified, any of characters 92-1 to 92-n is used, while a character 92 is used when an arbitrary SDRAM is to be indicated.
Also, regarding characters denoting the data signals, when one among the plurality of data signals needs to be specified, any of characters DQ-1 to DQ-n is used, while a character DQ is used when an arbitrary data signal is to be indicated.
Further, regarding characters denoting the data strobe signals, when one among the plurality of data strobe signals needs to be specified, any of characters DQS-1 to DQS-n is used, while a character DQS is used when an arbitrary data strobe signal is to be indicated.
Thus, in the DDR3 memory interface, because the clock signal line for the clock signal CK is wired to the plurality of SDRAMs 92-1 to 92-n through the daisy chain connection and a propagation delay is generated, the clock signal CK output from the memory controller 90 cannot reach all the SDRAMs 92-1 to 92-n at the same time. According to the JEDEC standards, for example, a length L1 of outer dimension of the DIMM module 91 is determined to be 133 mm. Assuming a data transmission speed to be 7 ps/mm, therefore, a difference of about 1 ns is generated in arrival time of the clock signal CK between the SDRAM 92-1 disposed at one end and the SDRAM 92-n disposed at the other end of the DIMM module 91 in the lengthwise direction thereof (namely, 7 ps/mm×133 mm=931 ps).
For that reason, according to the JEDEC standards, it is specified to employ the write leveling function in the DDR3 memory interface.
The term “write leveling function” refers to the function of sampling the clock signal CK by using the data strobe signal DQS output from the memory controller 90, detecting the phase relationship between the data strobe signal DQS and the clock signal CK, and adjusting (compensating) a delay time of the data strobe signal DQS. The write leveling function is realized, as shown in FIG. 2, by incorporating variable delay circuits 93-1 to 93-n, which can change respective delay times of the data strobe signals DQS-1 to DQS-n, in the memory controller 90 corresponding to the plurality of SDRAMs 92-1 to 92-n, respectively.
In the following description, regarding characters denoting the delay circuits, when one among the plurality of delay circuits needs to be specified, any of characters 93-1 to 93-n is used, while a character 93 is used when an arbitrary delay circuit is to be indicated.
More specifically, for the data strobe signals DQS-1 to DQS-n output respectively to the plurality of SDRAMs 92-1 to 92-n to which the clock signal line is wired through the daisy chain connection, a CPU (Central Processing Unit, not shown) sets respective delay times t1-1 to t1-n based on the data signals DQ-1 to DQ-n output from the plurality of SDRAMs 92-1 to 92-n so that the data strobe signals DQS-1 to DQS-n are adjusted to be input respectively to the plurality of SDRAMs 92-1 to 92-n substantially at the same time as the clock signal CK for each SDRAM.
In other words, for example, at the time of completion of the write leveling, the data strobe signals DQS are delayed through the respective delay times t1-1 to t1-n in the delay circuits 93-1 to 93-n which correspond to the SDRAMs 92-1 to 92-n on the DIMM module 91, respectively, whereby the data strobe signal DQS and the clock signal CK are input in phase to each of the SDRAMs 92-1 to 92-n. 
Thus, in the DDR3 memory interface, the difference in the delay time caused in the write operations between the memory controller 90 and the plurality of SDRAMs 92 is adjusted by employing the write leveling function.
Additionally, in the above-described case, the delay times t1-1 to t1-n are not equal to each other because the clock signal CK is input to the SDRAMs 92-1 to 92-n via the clock signal line through the daisy chain connection.
Although, the DDR3 memory interface compensates the arrival time when the data strobe signals DQS-1 to DQS-n arrive at the SDRAMs 92-1 to 92-n in the write operations according to the JEDEC standards as described above, compensations of the signal arrival time in read operations are not provided with the JEDEC standards.
FIG. 3 is a block diagram explaining the read operation of the conventional DDR3 memory interface.
The SDRAMs 92-1 though 92-n output data signals DQ-1 though DQ-n and the data strobe signals DQS-1 through DQS-n to the memory controller 90 on receiving the clock signal CK output from the memory controller 90 via the data signal line in the daisy chain connection in the read operation as shown in FIG. 3.
Therefore, the data signal DQ-n and the data strove signal DQS-n output from the SDRAM 92-n to which the clock signal CK is input lastly arrives at the memory controller 90 approximately 1 ns after the data signal DQ-1 and the data strobe signal DQS-1 output from the SDRAM 92-1 to which the clock signal CK is input firstly where the data transmission speed is 7 ps/mm as the case described above. 7 ps/mm×133 mm=931 ps.
The delay on the order of 1 ns will become greater than a typical data period of the DDR3 memory interface, at minimum 0.625 ns, so that the delay may affect in reading data from the SDRAM 92.